1. Field of Endeavor
The example embodiments relate to methods of forming improved gate dielectric structures useful in semiconductor processing, methods of forming semiconductor devices incorporating such gate dielectric structures and semiconductor devices that utilize such gate dielectric structures.
2. Description of the Related Art
Efforts to increase levels of integration in electronic devices including, for example, integrated circuits and display devices incorporating such integrated circuits, and reduce the overall size of the electronic devices have resulted in design rules that reflect decreasing critical dimensions. For example, more aggressive design rules may reduce the spacing of adjacent active regions within the devices and/or variations in conductor width, the spacing of electrode patterns, the thickness of dielectric layers and the sizing of dielectric structures formed during fabrication of such devices. One of the challenges facing process development engineers is defining processes for fabricating structures that comply with the design rules, exhibit satisfactory performance and are within the capabilities of the equipment and materials utilized in the fabrication.
As the width of the gate structures and the thickness of the gate dielectric materials are reduced, the etch processes conventionally utilized for forming the gate structures can damage the peripheral portions of the gate dielectric material, thereby reducing the effective density and increasing the likelihood of current leakage through such regions. Excessive gate leakage will tend to compromise the performance and/or the reliability of the resulting devices and is, therefore, a result to be reduced or avoided where possible.
One method for addressing the gate leakage issue is a Gate Poly Oxidation (“GPOX”) in which a peripheral portion of the gate electrode structure adjacent the gate dielectric is oxidized in order to increase the thickness of the peripheral portion of the gate dielectric pattern, thereby suppressing leakage paths through those regions. Although this method may improve the performance of the gate dielectric, oxidizing a portion of the gate electrode pattern, particularly those gate electrodes that incorporate one or more silicide materials, also tends to increase the resistance of the gate electrode. Increases in the gate electrode resistance, however, tends to impede the propagation of electrical signals through the semiconductor device and may thereby compromise the performance of the resulting device.